Power density matching circuits for power amplifiers

A semiconductor die comprising:

• a packaging substrate configured to receive a plurality of components;
• a plurality of connection pads formed on the packaging substrate;
• and
• a power density matching circuit including a supply node configured to receive a supply voltage;
• a differential node configured to receive a signal from a differential amplifier;
• a reference node configured to provide a bias signal to a reference transistor;
• an amplifying node configured to provide a bias signal to an amplifying transistor;
• and a temperature independent current translator with a first transistor and a third transistor coupled emitter to collector between the supply node and a ground and a second transistor and a fourth transistor coupled emitter to collector between the supply node and the ground, a collector of the first transistor coupled to the supply node, a base of the first transistor coupled to the differential node, a base of the third transistor coupled to a collector of the third transistor, an emitter of the third transistor coupled to the ground, a collector of the second transistor coupled to the supply node, a base of the second transistor coupled to the differential node, a base of the fourth transistor coupled to a collector of the fourth transistor and to the reference node, and an emitter of the fourth transistor coupled to the ground.

A wireless device comprising:

• a transceiver configured to process radio-frequency signals;
• an antenna in communication with the transceiver configured to facilitate transmission of an amplified radio-frequency signal;
• and
• a power amplifier module connected to the transceiver and configured to generate the amplified radio-frequency signal, the power amplifier module including a supply node configured to receive a supply voltage;
• a differential node configured to receive a signal from a differential amplifier;
• a reference node configured to provide a bias signal to a reference transistor;
• an amplifying node configured to provide a bias signal to an amplifying transistor;
• and a temperature independent current translator with a first transistor and a third transistor coupled emitter to collector between the supply node and a ground and a second transistor and a fourth transistor coupled emitter to collector between the supply node and the ground, a collector of the first transistor coupled to the supply node, a base of the first transistor coupled to the differential node, a base of the third transistor coupled to a collector of the third transistor, an emitter of the third transistor coupled to the ground, a collector of the second transistor coupled to the supply node, a base of the second transistor coupled to the differential node, a base of the fourth transistor coupled to a collector of the fourth transistor and to the reference node, and an emitter of the fourth transistor coupled to the ground.