Time multiplexing circuit applied to dc-dc converting system

A time multiplexing circuit, applied to a DC-DC converting system and use for receiving a first pulse-width modulation signal and a second pulse-width modulation signal and outputting a first reverse output signal and a second reverse output signal, the time multiplexing circuit comprising:

• a first NOR gate, configured to receive the first pulse-width modulation signal, a clock signal and a reverse clock related signal and output a boost state request signal;
• a second NOR gate, configured to receive the second pulse-width modulation signal, the clock signal and a clock related signal and output a buck-boost state request signal;
• a first inverter, coupled to the first NOR gate and configured to convert the boost state request signal into a reverse boost state request signal;
• a second inverter, coupled to the second NOR gate and configured to convert the buck-boost state request signal into a reverse buck-boost state request signal;
• a first D-type flip-flop, coupled to the first inverter and configured to receive the reverse boost state request signal and an input voltage and output a first time multiplex output signal and a first reverse time multiplex output signal respectively;
• a second D-type flip-flop, coupled to the second inverter and configured to receive the reverse buck-boost state request signal and the input voltage and output a second time multiplex output signal and a second reverse time multiplex output signal respectively;
• a third NOR gate, coupled to the first D-type flip-flop and configured to receive the first reverse time multiplex output signal and the boost state request signal and output another first time multiplex output signal;
• a NOR gate, coupled to the second D-type flip-flop and configured to receive the second reverse time multiplex output signal and the reverse buck-boost state request signal and output another second time multiplex output signal;
• an OR gate, coupled to the third NOR gate and configured to receive the another first time multiplex output signal and a reverse enable signal and output the first reverse output signal;
• and
• an AND gate, coupled to the NOR gate and configured to receive the another second time multiplex output signal and an enable signal and output the second reverse output signal.