Manufacturing method for amorphous silicon tft substrate

A manufacturing method for amorphous silicon TFT substrate, comprising steps of:

• step S1, providing a base substrate, and sequentially depositing an amorphous silicon layer, an N-type doped amorphous silicon layer, a first transparent conductive layer, and a source drain metal layer on the base substrate;
• step S2, coating a photoresist material on the source drain metal layer and performing a first mask process to form a first photoresist layer, wherein the first photoresist layer has a first photoresist pattern, a second photoresist pattern, and a third photoresist pattern which are sequentially increased in thickness;
• Step S3, performing a first etching process by using the first photoresist layer as a shielding layer to remove the amorphous silicon layer, the N-type doped amorphous silicon layer, and the first transparent conductive layer and the source drain metal layer that are not covered by the first photoresist layer, wherein an amorphous silicon active layer is obtained from the amorphous silicon layer corresponding to an underside of the first photoresist pattern and the second photoresist pattern, and a pixel electrode is obtained from the first transparent conductive layer corresponding to an underside of the third photoresist pattern;
• Step S4, performing a first ashing treatment on the first photoresist layer, thinning the second photoresist pattern and the third photoresist pattern, and removing the first photoresist pattern;
• Step S5, performing a second etching process using the first photoresist layer as a shielding layer to remove the N-type doped amorphous silicon layer, the first transparent conductive layer, and the source drain metal layer that are not covered by the first photoresist layer, wherein a source electrode and a drain electrode are obtained from the source drain metal layer located above two ends of the amorphous silicon active layer and corresponding to an underside of the second photoresist pattern, and a source-drain contact region is obtained from the N-type doped amorphous silicon layer corresponding to an underside of the source electrode and the drain electrode;
• Step S6, performing a second ashing treatment to the first photoresist layer, thinning the third photoresist pattern and removing the second photoresist pattern;
• Step S7, performing a third etching process by using the first photoresist layer as a shielding layer, and removing the source drain metal layer corresponding to an upside of the pixel electrode to expose the pixel electrode, and peeling off a remaining portion of the first photoresist layer;
• Step S8, depositing a passivation layer that covers the amorphous silicon active layer, the source electrode, the drain electrode, and the pixel electrode on the base substrate, through a second mask process, forming a first via and a second via respectively corresponding to the drain electrode and the pixel electrode on the passivation layer;
• Step S9, sequentially depositing a second transparent conductive layer and a gate metal layer on the passivation layer, coating a photoresist material on the source drain metal layer and performing a third mask process to form a second photoresist layer, wherein the second photoresist layer has a fourth photoresist pattern and a fifth photoresist pattern which are sequentially increased in thickness;
• Step S10, performing a first etching process using the second photoresist layer as a shielding layer to remove the second transparent conductive layer and the gate metal layer which are not covered by the second photoresist layer, wherein corresponding to an underside of the fourth photoresist pattern, a gate electrode and a metal common electrode line separated from the gate electrode which are corresponding to an upside of the amorphous silicon active layer are obtained;
• corresponding to an underside of the fifth photoresist pattern, a conductive connection block and a transparent common electrode line separated from the conductive connection block are obtained from the second transparent conductive layer;
• wherein the conductive connection block is contacted with the drain electrode and the pixel electrode respectively through the first via and the second via in order to electrically conduct the drain electrode and the pixel electrode;
• Step S11, performing a first ashing treatment to the second photoresist layer, thinning the fifth photoresist pattern and removing the fourth photoresist pattern;
• and
• Step S12, performing a second etching process using the second photoresist layer as a shielding layer to remove the gate metal layer corresponding to an upside of the conductive connection block and the transparent common electrode line, and peeling off a remaining portion of the second photoresist layer.