US 2019/0355834 A1 · VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR ON SILICON WITH DEFINED JUNCTIONS

Abstract

A method for fabricating a semiconductor structure includes the following steps. A plurality of dielectric layers is formed on a substrate, wherein the material composition and layer positioning of each of the plurality of dielectric layers are selected to enable defined junctions for one or more features of the semiconductor structure. A trench is formed through each of the plurality of dielectric layers to the top of the substrate, wherein the height and width dimensions of the trench are selected in accordance with an aspect ratio trapping process. A vertical fin structure is formed by epitaxially growing material within the trench on the top of the substrate. In further steps, gate stack and source/drain regions are formed around the vertical fin structure in accordance with the positioning of the plurality of dielectric layers. The resulting semiconductor structure, in one or more examples, is a vertical transport field-effect transistor.

Claims20

Dependent claims

A semiconductor structure, comprising:

a silicon substrate;
a non-silicon vertical fin structure formed on the silicon substrate using an aspect ratio trapping process;
a gate stack, a first source/drain region, and a second source/drain region disposed at defined locations by a plurality of dielectric layers formed on the silicon substrate and selectively removed;
and
metal contacts to electrically couple respectively with the gate stack, the first source/drain region, and the second source/drain region.

2 more elements

Dependencies are inferred from the claim text.

Vertical transport field effect transistor on silicon with defined junctions

Life of this patent

Vertical transport field effect transistor on silicon with defined junctions

Life of this patent

Abstract

Claims20