Stacked vertical transport field effect transistor electrically erasable programmable read only memory (eeprom) devices

An electrically erasable programmable read-only memory (EEPROM) array, comprising:

• a plurality of stacked vertical transport field effect transistors (VT FETs), wherein the stacked VT FETs each include an n-type vertical transport field effect transistor and a p-type vertical transport field effect transistor collinear with one another;
• a first bit line connected to a source of at least one of the n-type vertical transport field effect transistors;
• a second bit line connected to a source of at least one of the p-type vertical transport field effect transistors;
• and
• a word line connected to a common drain of the at least one n-type vertical transport field effect transistor and the at least one p-type vertical transport field effect transistor.

A method of forming a vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET), comprising:

• forming a first bottom source/drain layer on a substrate, wherein the first bottom source/drain layer has a first conductivity type;
• forming a lower channel layer on the first bottom source/drain layer;
• forming a first top source/drain layer on the lower channel layer, wherein the first top source/drain layer has the first conductivity type;
• forming a second bottom source/drain layer on the first top source/drain layer, wherein the second bottom source/drain layer has a second conductivity type different from the first conductivity type;
• forming an upper channel layer on the second bottom source/drain layer;
• forming a second top source/drain layer on the upper channel layer, wherein the second top source/drain layer has the second conductivity type different from the first conductivity type;
• forming one or more fin templates on the second top source/drain layer;
• and
• removing the portions of the second top source/drain layer and the other underlying layers not covered by the one or more fin templates down to the first bottom source/drain layer to form one or more vertically stacked sets of channel pillars and source/drains.