Semiconductor apparatus

A semiconductor device comprising an MIS structure including:

• a semiconductor layer having a front surface and a rear surface;
• a gate insulating film formed on the front surface side in the semiconductor layer;
• and
• a gate electrode formed on the gate insulating film,
• wherein the gate insulating film has a layered structure that includes a base SiO2 layer and a high-k layer on the base SiO2 layer and containing Hf, and
• the gate electrode has a portion made of a metal material having a work function of higher than 4.6 eV, the portion being in contact with at least the high-k layer.

A semiconductor device comprising an MIS structure including:

• a semiconductor layer having a front surface and a rear surface;
• a gate insulating film formed on the front surface side in the semiconductor layer;
• and
• a gate electrode formed on the gate insulating film,
• wherein the gate insulating film has a layered structure that includes a base SiO2 layer, a high-k layer on the base SiO2 layer and containing Hf, and an upper insulating layer between the high-k layer and the gate electrode, and
• the upper insulating layer is made of a material having a difference of lower than 4 eV between a lowest energy Ec in the conduction band and a vacuum energy level.

A semiconductor device comprising an MIS structure including:

• a semiconductor layer having a front surface and a rear surface;
• a gate insulating film formed on the front surface side in the semiconductor layer;
• and
• a gate electrode formed on the gate insulating film,
• wherein the gate insulating film has a layered structure that includes a base SiO2 layer and a high-k layer on the base SiO2 layer and containing Hf, and
• the gate electrode has a portion made of Mo, Cu, Au, Ni, Pt or TiN, the portion being in contact with at least the high-k layer.

A semiconductor device comprising an MIS structure including:

• a semiconductor layer having a front surface and a rear surface;
• a gate insulating film formed on the front surface side in the semiconductor layer;
• and
• a gate electrode formed on the gate insulating film,
• wherein a variation rate of a post-test threshold voltage after a negative stress voltage of a predetermined magnitude is applied to the gate electrode for 30 minutes or longer to an initial threshold voltage of the gate electrode is within 20%.