Finfet devices with a fin top hardmask
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Cheng Ching, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Abstract
Aspects of the disclosure provide a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.
Claims21
A semiconductor device, comprising:
- a substrate;
- a fin over the substrate;
- a fin top hardmask over a top surface of a channel region of the fin;
- a gate stack straddling the fin and the fin top hardmask;
- a pair of spacers disposed over the fin and adjacent to opposite sidewalls of the gate stack;
- and
- a source/drain region disposed adjacent to one of the pair of spacers.
A fin field effect transistor (FinFET), comprising:
- a fin top hardmask on a top surface of a channel region of a fin;
- and
- a gate stack straddling the fin and the fin top hardmask, the gate stack including a top portion that includes a horizontally spreading metal-containing layer, and a lower portion that includes a gate dielectric layer and a work function tuning layer over the gate dielectric layer.
-20. (canceled)
A semiconductor device, comprising:
- a substrate;
- a fin over the substrate;
- a pad layer over a top surface of a channel region of the fin;
- a gate stack including a gate dielectric layer and straddling the fin and the pad layer;
- a pair of spacers disposed over the fin and respectively adjacent to opposite sidewalls of the gate stack;
- and
- a source/drain region disposed adjacent to one of the spacers.
Dependencies are inferred from the claim text.