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US 2019/0355818 A1Published application
Steep sloped vertical tunnel field-effect transistor
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPeter Ramvall, Matthias Passlack
Life of this patent
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Abstract
The current disclosure describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer.
Claims21
A structure, comprising:
- a substrate;
- a first gallium nitride layer in gallium polar over the substrate;
- a mask layer over the first gallium nitride layer, the mask layer including an aperture;
- a second gallium nitride layer in gallium polar overlaying the first gallium nitride layer through the aperture, the second gallium nitride layer having six sloped surfaces;
- a layer of one or more of indium gallium nitride or indium nitride overlaying the second gallium nitride layer;
- and
- a third gallium nitride layer in gallium polar overlaying the layer of one or more of indium gallium nitride or indium nitride, the third gallium nitride layer having a substantially flat upper surface.
4 more elements
A device, comprising:
- a gallium nitride base;
- a first nanowire source/drain region of gallium nitride overlaying the gallium nitride base;
- an intermediate region of a III-V semiconductor material different from GaN overlaying the first nanowire source/drain region;
- a second nanowire source/drain region of gallium nitride overlaying the intermediate region of the III-V semiconductor material;
- and
- a gate structure adjacent to the intermediate region.
3 more elements
18-20. (canceled)
A semiconductor structure, comprising:
- a substrate;
- a first gallium nitride layer over the substrate, the first gallium nitride layer including a first impurity of a first electronic conductivity type;
- a second gallium nitride layer over the first gallium nitride layer, the second nanowire gallium nitride layer including a second impurity of the first electronic conductivity type;
- a layer of one of more of indium nitride or indium gallium nitride over the second gallium nitride layer;
- a third gallium nitride layer over the layer of one or more of indium nitride or indium gallium nitride, the third gallium nitride layer including a third impurity of a second electronic conductivity type that is different from the first electronic conductivity type;
- and
- a gate structure adjacent to the layer of one or more of indium nitride or indium gallium nitride;
- wherein a sidewall of the second gallium nitride layer, a sidewall of the third gallium nitride layer and a sidewall of the layer of one of more of indium nitride or indium gallium nitride are substantially plumb among one another.
5 more elements
Dependencies are inferred from the claim text.