Thin film transistor substrate, method of manufacturing the same, and display device including the same

A method of manufacturing a thin film transistor substrate, comprising:

• forming a first active pattern on a base substrate;
• forming a first gate insulation layer at least partially covering the first active pattern;
• forming a first gate electrode on the first gate insulation layer, the first gate electrode forming a first thin film transistor with the first active pattern;
• forming a second gate insulation layer at least partially covering the first gate electrode;
• forming a second gate electrode on the second gate insulation layer, the second gate electrode at least partially overlapping the first gate electrode;
• forming a source connection electrode in contact with a source region of the first active pattern;
• forming a drain connection electrode in contact with a drain region of the first active pattern;
• forming a first insulation interlayer at least partially covering the second gate electrode;
• forming a second active pattern on the first insulation layer;
• forming a third gate insulation layer at least partially covering the second active pattern;
• forming a third gate electrode on the third gate insulation layer, the third gate electrode forming a second thin film transistor with the second active pattern;
• forming a second insulation interlayer at least partially covering the third gate electrode;
• and
• forming each of a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode on the second insulation interlayer, the first source electrode and the first drain electrode contacting the source connection electrode and the drain connection electrode, respectively, and the second source electrode and the second drain electrode contacting a source region and a drain region of the second active pattern, respectively.

A display device, comprising:

• a base substrate;
• a first active pattern disposed on the base substrate;
• a first gate insulation layer at least partially covering the first active pattern;
• a first gate electrode disposed on the first gate insulation layer, the first gate electrode forming a first thin film transistor with the first active pattern;
• a second gate insulation layer at least partially covering the first gate electrode;
• a second gate electrode disposed on the second gate insulation layer, the second gate electrode at least partially overlapping the first gate electrode;
• a source connection electrode contacting a source region of the first active pattern;
• a drain connection electrode contacting a drain region of the first active pattern;
• a first insulation interlayer at least partially covering the second gate electrode;
• a second active pattern disposed on the first insulation layer;
• a third gate insulation layer at least partially covering the second active pattern;
• a third gate electrode disposed on the third gate insulation layer, the third gate electrode forming a second thin film transistor with the second active pattern;
• a second insulation interlayer at least partially covering the third gate electrode;
• a first source-drain pattern disposed on the second insulation interlayer, the first source-drain pattern including a first source electrode and a first drain electrode contacting the source connection electrode and the drain connection electrode, respectively, and a second source electrode and a second drain electrode contacting a source region and a drain region of the second active pattern, respectively;
• a first planarization layer at least partially covering the first source-drain pattern;
• and
• a light emitting structure disposed on the first planarization layer, the light emitting structure being electrically connected to the first thin film transistor.