Bit cost scalable 3d phase change cross-point memory
AssigneeMacronix International Co., Ltd.
InventorsHsiang-Lan LUNG, Erh-Kun LAI, Ming-Hsiu LEE, Chiao-Wen YEH
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Abstract
An integrated circuit includes a three-dimensional cross-point memory having a plurality of levels of memory cells disposed in cross points of first access lines and second access lines with alternating wide and narrow regions. The manufacturing process of the three-dimensional cross-point memory includes patterning with three patterns: a first pattern to define the memory cells, a second pattern to define the first access lines, and a third pattern to define the second access lines.
Claims20
A memory, comprising:
- a plurality of first access lines extending in a first direction in a first access line layer, the first access lines having alternating wide regions and narrow regions;
- a plurality of second access lines extending in a second direction in a second access line layer, the second access lines having alternating wide regions and narrow regions, wide regions in second access lines of the plurality of second access lines overlying wide regions in first access lines of the plurality of first access lines at cross-points between the first and second access lines;
- and
- an array of memory cells disposed in the cross-points between the first and second access lines.
A method of manufacturing an integrated circuit, comprising:
- forming a plurality of first access lines extending in a first direction in a first access line layer, the first access lines having alternating wide regions and narrow regions;
- forming a plurality of second access lines extending in a second direction in a second access line layer, the second access lines having alternating wide regions and narrow regions, wide regions in second access lines of the plurality of second access lines overlying wide regions in first access lines of the plurality of first access lines at cross-points between the first and second access lines;
- and
- forming an array of memory cells disposed in the cross-points between the first and second access lines.
A method of manufacturing an integrated circuit, comprising:
- forming a first stack of materials, including layers of a first conducting material, layers of a programmable memory material, and layers of a second conducting material;
- etching first holes defined by a first hole pattern through the first stack;
- selectively laterally etching the layers of the programmable memory material through the first holes to form an array of memory cells;
- forming a first insulating fill in the first holes;
- etching second holes defined by a second hole pattern through the first stack;
- selectively laterally etching the layers of the first conducting material through the second holes to form a plurality of first access lines extending in a first direction, the first access lines having alternating wide regions and narrow regions;
- forming a second insulating fill in the second holes;
- and
- etching third holes defined by a third hole pattern through the first stack;
- and
- selectively laterally etching the layers of the second conducting material through the third holes to form a plurality of second access lines extending in a second direction, the second access lines having alternating wide regions and narrow regions and wide regions in second access lines of the plurality of second access lines overlying wide regions in first access lines of the plurality of first access lines at cross-points between the first and second access lines.
Dependencies are inferred from the claim text.