Staggered Word Line Architecture for Reduced Disturb in 3-Dimensional NOR Memory Arrays

A memory structure, comprising:

• A plurality of memory cells sharing a common bit line that extends along a first direction, wherein a first group of the memory cells are provided along the first direction on a first side of the common bit line, wherein a second group of the memory cells are provided along the first direction on a second side of the common bit line opposite the first side, each memory cell of either group being separated from each adjacent memory cell of the same group by a predetermined distance and from each memory cell of the other group by at least one half the predetermined distance, as measured along the first direction, and wherein each memory cell comprises a storage layer;
• and
• a first plurality of conductors each extending along a second direction substantially perpendicular to the first direction, wherein a first group of the first plurality of conductors are each provided adjacent a corresponding one of the first group of memory cells and wherein a second group of the first plurality of conductors are each provided adjacent a corresponding one of the second group of memory cells, such that the conductor serves as a gate electrode for its corresponding memory cell and controls an amount of charge stored in the storage layer of the corresponding memory cell.