US 2019/0355746 A1 · 3D MEMORY DEVICE

Abstract

A 3D memory device, comprising a plurality of rows of strings of memory cells, each row of strings of memory cells comprising an array of strings of memory cells extending along a first direction, the rows following one another along a second direction. Each string of memory cells comprises a stack of memory cells, and the strings of memory cells of the stack extend in a third direction from a first end to a second end. A source region is provided at the second end of the strings of memory cells. Consecutive rows of strings of memory cells along the second direction are spaced apart from each other of a pitch. Between pairs of strings of a row of memory cells along the second direction there is formed a slit extending in the third direction from the first end down to the source region. The slit has dimension, along the second direction, smaller than, equal to or greater than the pitch, sufficient to the formation, in the slit, of an electrical contact to the source region.

Claims7

Dependent claims

-8. (canceled)

A method of making a three-dimensional, 3D, memory device comprising:

forming a plurality of rows of strings of memory cells, each row of strings of memory cells comprising an alignment of strings of memory cells extending along a first direction, said rows following one another along a second direction, wherein each string of memory cells comprises a stack of memory cells, said strings of memory cells of the stack extending along a third direction from a first end to a second end, wherein rows of strings of memory cells consecutive along said second direction are spaced apart from each other of a pitch;
forming a source region at the second end of the strings of memory cells;
forming, between pairs of said rows of strings of memory cells consecutive along said second direction, a slit extending in said third direction from said first end to said source region, wherein said slit has size, along said second direction, less, equal or greater than said pitch sufficient for the formation, in said slit, of an electrical contact to the source region;
forming said electrical contact to the source region.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

16/529,648Filed 1 Aug 2019

Priority

IT 10201700001939221 Feb 2017

Published

21 Nov 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout

3d memory device

Life of this patent

3d memory device

Life of this patent

Abstract

Claims7