US 2019/0355740 A1 · 3D SEMICONDUCTOR DEVICES INCLUDING A SUPPORTER AND METHODS OF FORMING THE SAME

Abstract

A semiconductor device comprises a lower conductive layer on a substrate. A conductive line is on the lower conductive layer. A buried trench in the conductive line is provided. A supporter which is on the conductive line and extends in the buried trench is provided. A stack structure including a plurality of insulating layers and a plurality of conductive layers that are alternately stacked is on the supporter. A channel structure passing through the stack structure, the supporter, and the conductive line is provided. An isolation trench passing through the stack structure, the supporter, and the conductive line is provided.

Claims21

Dependent claims

A semiconductor device comprising:

a lower conductive layer on a substrate;
a conductive line on the lower conductive layer;
a buried trench in the conductive line;
a supporter on the conductive line and extending in the buried trench;
a stack structure comprising a plurality of insulating layers and a plurality of conductive layers that are alternately stacked on the supporter;
a channel structure that passes through the stack structure, the supporter, and the conductive line;
and
an isolation trench that passes through the stack structure, the supporter, and the conductive line.

5 more elements

A semiconductor device comprising:

a substrate comprising a cell region and a pad region adjacent to the cell region;
a lower conductive layer on the substrate;
a mold layer in the pad region on the lower conductive layer;
a conductive line in the cell region on the lower conductive layer and at a substantially same level as the mold layer;
a first extension buried trench in the mold layer;
a second extension buried trench spaced apart from the first extension buried trench and in the mold layer;
a supporter on the conductive line and the mold layer and extending in the first extension buried trench and the second extension buried trench;
a stack structure comprising a plurality of insulating layers and a plurality of conductive layers that are alternately stacked on the supporter;
a plurality of cell channel structures that pass through the stack structure, the supporter, and the conductive line;
a plurality of dummy channel structures that pass through the stack structure, the supporter, and the mold layer between the first extension buried trench and the second extension buried trench;
and
a plurality of isolation trenches that pass through the stack structure, the supporter, and the conductive line.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/192,232Filed 15 Nov 2018

Priority

KR 10-2018-005763621 May 2018

Published

21 Nov 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/20
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by three-dimensional [3D] arrangements, e.g.…
H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND
H10B 41/41
Characterised by the peripheral circuit region: of a memory region comprising a cell select transistor, e.g. NAND

3d semiconductor devices including a supporter and methods of forming the same

Life of this patent

3d semiconductor devices including a supporter and methods of forming the same

Life of this patent

Abstract

Claims21