Semiconductor device

A semiconductor device, comprising:

• a stacked structure disposed on a substrate, wherein the stacked structure comprises a plurality of gate electrodes;
• a plurality of main separation lines passing through the stacked structure in a first direction substantially perpendicular to an upper surface of the substrate, extending in a second direction substantially parallel to the upper surface of the substrate and intersecting the stacked structure, and having edge end portions located outside of the stacked structure;
• a plurality of first secondary separation lines passing through the stacked structure in the first direction, extending in the second direction, and having edge end portions located on outer sides of the stacked structure;
• a plurality of second secondary separation lines passing through the stacked structure in the first direction, and having inside end portions facing the first secondary separation lines;
• and
• a structure facing the edge end portions of the main separation lines and the edge end portions of the first secondary separation lines,
• wherein upper surfaces of the structure are coplanar with upper surfaces of the main separation lines and upper surfaces of the first secondary separation lines.

A semiconductor device, comprising:

• a memory array region disposed on a substrate, and an extension region disposed adjacent to the memory array region;
• a stacked structure disposed in the memory array region and the extension region,
• wherein the stacked structure comprises a plurality of gate electrodes spaced apart from one another and stacked in a first direction in the memory array region,
• wherein the first direction is substantially perpendicular to an upper surface of the substrate,
• wherein the gate electrodes extend into the extension region and comprise a plurality of pads disposed in a stepped shape in the extension region;
• a plurality of memory vertical structures extending in the first direction and passing through the gate electrodes in the memory array region;
• a plurality of main separation lines intersecting the memory array region and the extension region and separating the stacked structure in a second direction;
• a plurality of secondary separation lines passing through the stacked structure in the extension region;
• and
• a structure disposed on the substrate and disposed outside of the stacked structure,
• wherein the main separation lines and the secondary separation lines comprise edge end portions extending in a third direction from the extension region and located on outer sides of the stacked structure,
• wherein the structure comprises outer side end portions facing the edge end portions, wherein upper surfaces of the main separation lines, the secondary separation lines, and the structure are coplanar with one another and formed of the same material.