Method to reduce kink effect in semiconductor devices

A method for forming a semiconductor device, the method comprising:

• forming a pad stack over a semiconductor substrate, wherein the pad stack comprises a lower pad layer and an upper pad layer;
• patterning the upper pad layer and the lower pad layer into a patterned upper pad layer and a patterned lower pad layer, respectively;
• forming an isolation structure in the semiconductor substrate, wherein the isolation structure comprises a first isolation structure segment and a second isolation structure segment separated by the patterned upper pad layer and the patterned lower pad layer;
• removing the patterned upper pad layer to form an opening between the first isolation structure segment and the second isolation structure segment, wherein the opening is defined by opposing sidewalls of the first and second isolation structure segments;
• performing a first etch to partially remove the patterned lower pad layer between the first and second isolation structure segments, and to partially remove the first and second isolation structure segments through the opening, wherein the first etch increases a lateral separation between the opposing sidewalls more at a top of the opening than at a bottom of the opening;
• performing a second etch to arch the opposing sidewalls and to remove the patterned lower pad layer between the first and second isolation structure segments;
• and
• forming a first floating gate between the first and second isolation structure segments.

A method for forming a semiconductor device, the method comprising:

• forming a control gate over a semiconductor substrate;
• forming a floating gate between the control gate and the semiconductor substrate, wherein the floating gate is formed with a bottom surface extending in a first lateral direction that is substantially planar, and wherein the floating gate is formed with a pair of arching sidewalls spaced apart in a second lateral direction perpendicular to the first lateral direction;
• forming a first source/drain region in the semiconductor substrate and on a first side of the floating gate;
• forming an erase gate directly over the first source/drain region;
• forming a select gate over the semiconductor substrate and on a second side of the floating gate opposite the first side, wherein the first side and the second side are spaced apart in the first lateral direction;
• and
• forming a second source/drain region in the semiconductor substrate and on the second side of the floating gate.