Static random access memory cells with arranged vertical-transport field-effect transistors

A structure comprising:

• a first active device region;
• a second active device region;
• and
• a storage element including a first pull-up (PU) vertical-transport field-effect transistor (VTFET) with a first bottom source/drain region centrally arranged in the first active device region and a fin projecting from the first bottom source/drain region, a first pull-down (PD) vertical-transport field-effect transistor (VTFET) with a fin projecting from the first active device region and aligned lengthwise in a first row with the fin of the first PU VTFET, a second pull-up (PU) vertical-transport field-effect transistor (VTFET) with a second bottom source/drain region centrally arranged in the first second active device region and a fin projecting from the second bottom source/drain region, and a second pull-down (PD) vertical-transport field-effect transistor (VTFET) with a fin projecting from the second active device region and aligned lengthwise in a second row with the fin of the second PU VTFET,
• wherein the first bottom source/drain region of the first PU VTFET in the first active device region is aligned with the second bottom source/drain region of the second PU VTFET in the second active device region such that the first bottom source/drain region and the second bottom source/drain region are laterally arranged between the first PD VTFET and the second PD VTFET.