Integrated circuit device

An integrated circuit device comprising:

• a substrate having a cell array area and a peripheral circuit area, the cell array area comprising a plurality of first active regions spaced apart from each other, and the peripheral circuit area comprising a second active region;
• a plurality of direct contacts each connected to a corresponding one of the plurality of first active regions in the cell array area;
• a plurality of bit line structures extending parallel to each other in a first direction in the cell array area, each of the plurality of bit line structures is connected to a corresponding one of the plurality of direct contacts;
• and
• a peripheral circuit gate structure on the second active region in the peripheral circuit area,
• wherein the peripheral circuit gate structure comprises two doped semiconductor layers each doped with a charge carrier impurity and having different doping concentrations from each other, and
• wherein each of the plurality of direct contacts comprises a contact semiconductor layer having a doping concentration that is lower than a doping concentration of at least one of the two doped semiconductor layers.

An integrated circuit device comprising:

• a substrate having a cell array area and a peripheral circuit area, the cell array area comprising a first active region, and the peripheral circuit area comprising a second active region;
• a direct contact connected to the first active region in the cell array area and comprising a doped contact semiconductor layer doped with a charge carrier impurity that has a first doping concentration;
• a bit line structure over the substrate in the cell array area, the bit line structure comprising a bit line semiconductor layer that contacts a top surface of the direct contact and has a doping concentration higher than the first doping concentration;
• a direct contact spacer contacting a first sidewall portion of a sidewall of the direct contact and comprising an undoped semiconductor having no charge carrier impurity doped thereon, the first sidewall portion being between the substrate and the bit line structure;
• an insulating spacer contacting a second sidewall portion of the sidewall of the direct contact and covering a sidewall of the bit line structure;
• and
• a peripheral circuit gate structure on the second active region in the peripheral circuit area, wherein the peripheral circuit gate structure comprises a first gate semiconductor layer and a second gate semiconductor layer, the first gate semiconductor layer having a doping concentration that is equal to or higher than the first doping concentration, and the second gate semiconductor layer having a doping concentration that is higher than the first doping concentration.