US 2019/0355719 A1Published application

Semiconductor device

AssigneeSamsung Electronics Co., Ltd.

InventorsShigenobu MAEDA, Sung Chul PARK, Chul Hong PARK, Yoshinao HARADA, Sung Min KANG, Ji Wook KWON, Ha-Young KIM, Yuichi HIRANO

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Abstract

A semiconductor device includes first to fourth cells sequentially disposed on a substrate, first to third diffusion break structures, a first fin structure configured to protrude from the substrate, the first fin structure comprising first to fourth fins separated from each other by the first to third diffusion break structures, a second fin structure configured to protrude from the substrate, to be spaced apart from the first fin structure, the second fin structure comprising fifth to eighth fins separated from each other by the first to third diffusion break structures, the first to fourth gate electrodes being disposed in the first to fourth cells, respectively, and the number of fins in one cell of the first to fourth cells is different from the number of fins in an other cell of the first to fourth cells.

Claims20

Dependent claims

A semiconductor device comprising:

first to fourth cells sequentially disposed on a substrate in a first direction;
first to third diffusion break structures configured to space the first to fourth cells apart from each other, the first diffusion break structure being interposed between the first and second cells, the second diffusion break structure being interposed between the second and third cells, and the third diffusion break structure being interposed between the third and fourth cells;
a first fin structure configured to protrude from the substrate and extend in the first direction, the first fin structure comprising first to fourth fins separated from each other by the first to third diffusion break structures;
a second fin structure configured to protrude from the substrate, to be spaced apart from the first fin structure in a second direction intersecting the first direction and extend in the first direction, the second fin structure comprising fifth to eighth fins separated from each other by the first to third diffusion break structures;
and
first to fourth gate electrodes configured to extend in the second direction on the first and second fin structures, the first to fourth gate electrodes being disposed in the first to fourth cells, respectively,
wherein each of the first to fourth gate electrodes intersects the first fin structure at an n region of the substrate and the second fin structure at a p region of the substrate, and
the number of fins in each of the first, second, and fourth cells is two.

5 more elements

A semiconductor device comprising:

a substrate;
a first power rail and a second power rail configured to extend in a first direction on the substrate, the first and second power rails being spaced apart from each other in a second direction intersecting the first direction;
a first fin configured to protrude from the substrate and extend in the first direction;
a second fin configured to protrude from the substrate and extend in the first direction, the second fin being spaced apart from the first fin in the second direction;
a first diffusion break structure and a second diffusion break structure configured to define both ends of the first and second fins;
and
a gate electrode configured to extend on the first and second fins in the second direction,
wherein the first fin is a fin nearest to the first power rail in the second direction, the second fin is a fin nearest to the second power rail in the second direction, and the first fin and the second fin have no fins between them in the second direction.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/372,166Filed 1 Apr 2019
Priority: KR 10-2018-005653817 May 2018
Published: 21 Nov 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 84/834
Of only insulated-gate FETs [IGFET]: comprising FinFETs
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 30/6215
Fin field-effect transistors [FinFET]: having multiple independently-addressable gate electrodes

Family

US 10,840,244 B2Related patent
US 2019/0355719 A1This patent

From the US filing history. Foreign family members aren’t listed.

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