Semiconductor packages relating to thermal redistribution patterns

A semiconductor package comprising:

• a first semiconductor chip and a second semiconductor chip disposed side by side on a package substrate;
• and
• a thermal redistribution pattern including a first end portion, a second end portion and a plurality of sub-extension portions,
• the first end portion disposed over a high temperature region adjacent to the first semiconductor chip,
• the second end portion disposed over a low temperature region adjacent to the second semiconductor chip,
• the plurality of sub-extension portions arrayed along a path with extending horizontally over the package between the first end portion and the second end portion,
• the plurality of sub-extension portions arrayed to pass by the second semiconductor chip to detour the second semiconductor chip, and
• the plurality of sub-extension portions spaced part from each other.

A semiconductor package comprising:

• a first semiconductor chip and a second semiconductor chip disposed side by side on a package substrate;
• and
• a thermal redistribution pattern including a first end portion, a second end portion and an extension portion,
• the first end portion disposed adjacent to the first semiconductor chip,
• the second end portion disposed adjacent to the second semiconductor chip,
• the extension portion connected to the first end portion and the second end portion, and configured to reduce a bottleneck phenomenon of heat transmission when transferring heat from the first end portion to the second end portion, and
• the extension portion extending horizontally over the package substrate and passing by the second semiconductor chip to detour the second semiconductor chip.