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US 2019/0355615 A1Published application
Methods, apparatus, and system for a semiconductor device comprising gates with short heights
AssigneeGlobalfoundries Inc.
InventorsJiehui Shu, Garo Jacques Derderian, Hui Zang, John Zhang, Haigou Huang, Jinping Liu
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Abstract
At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.
Claims18
-7. (Canceled)
A semiconductor device, comprising:
- a semiconductor substrate;
- an active area disposed on the semiconductor substrate;
- a shallow trench isolation (STI) disposed in the silicon substrate adjacent to the active area;
- a gate disposed over the active area and the STI;
- a first spacer disposed on one gate sidewall and a second spacer disposed on another gate sidewall, wherein a top of the gate is below a top of the first spacer and a top of the second spacer;
- and
- a silicon nitride cap disposed on the gate, on the top of the first spacer, and on the top of the second spacer.
4 more elements
A system, comprising:
- a semiconductor device processing system to manufacture a semiconductor device;
- and
- a processing controller operatively coupled to the semiconductor device processing system, the processing controller configured to control an operation of the semiconductor device processing system;
- wherein the semiconductor device processing system is adapted to:
- form a gate over at least one active area disposed on a semiconductor substrate;
- form a first spacer disposed on one gate sidewall and a second spacer disposed on another gate sidewall;
- form a dielectric material adjacent the first spacer and adjacent the second spacer;
- recess the gate to below a top of the first spacer and a top of the second spacer;
- form a silicon nitride liner on a top of the recessed gate;
- grow a silicon nitride cap selectively on the silicon nitride liner and at least on a top of the first spacer and a top of the second spacer;
- and
- form contacts to the gate and the active area, wherein contact formation is self-aligned by the silicon nitride cap.
9 more elements
A semiconductor device, comprising:
- a semiconductor substrate;
- an active area disposed on the semiconductor substrate;
- a shallow trench isolation (STI) disposed in the silicon substrate adjacent to the active area;
- a gate disposed over the active area and the STI;
- a first spacer disposed on one gate sidewall and a second spacer disposed on another gate sidewall, wherein a top of the gate is below a top of the first spacer and a top of the second spacer;
- a source disposed over the active area and the STI and adjacent to a first side of the gate;
- and
- a drain disposed over the active area and the STI and adjacent to a second side of the gate;
- a dielectric material disposed over the source over the STI and over the drain over the STI;
- and
- a silicon nitride cap disposed on the gate, on the top of the first spacer, on the top of the second spacer, on a portion of a top of dielectric material disposed over the source, and on a portion of a top of dielectric material disposed over the drain.
8 more elements
Dependencies are inferred from the claim text.