Method of forming drain extended mos transistors for high voltage circuits

A method comprising:

• forming a first threshold voltage adjust mask over a surface of a substrate to expose a high-voltage metal-on-semiconductor (HV_MOS) transistor in a high-voltage metal-on-semiconductor (HV_MOS) region of the substrate, and to expose a drain portion of a drain extended metal-on-semiconductor (DE_MOS) transistor in a DE_MOS region of the substrate;
• implanting ions of a first-type at a first energy level in the drain portion of the DE_MOS transistor, while concurrently implanting ions of the first-type at the first energy level in the HV_MOS transistor to adjust a voltage threshold of the HV_MOS;
• forming a second threshold voltage adjust mask over the surface of a substrate to expose a low-voltage metal-on-semiconductor (LV_MOS) transistor in a low-voltage metal-on-semiconductor (LV_MOS) region of the substrate, and to expose the drain portion of the DE_MOS transistor;
• and
• implanting ions of the first-type at a second energy level in the drain portion of the DE_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the LV_MOS transistor to adjust a voltage threshold of the LV_MOS.