Method and circuit for de-biasing puf bits

A method of reducing sense-amplifier bias in generating a physically unclonable function (PUF) signature comprising:

• providing an array of bit generating cells arranged in a plurality of rows and columns, each bit generating cell associated with a respective row and column combination;
• coupling through a column multiplexer a first set of the columns to a first sense amplifier;
• selecting a row;
• sensing using the first sense amplifier multiple bits from the bit generating cells in the selected row and associated with the first set of columns;
• and
• producing an output for generating a PUF signature that is dependent on the multiple bits using a logic operation that reduces the sense amplifier bias of the first sense amplifier.

An integrated circuit device comprising:

• an array comprising a plurality of bit generating cells arranged in a plurality of rows and columns, each bit generating cell associated with a respective row and column combination, each column corresponding to a respective bitline pair coupled to bit generating cells in the column;
• a physically unclonable function (PUF) generator, comprising:
• a plurality of column multiplexers, each column multiplexer coupled to a respective set of columns from the array;
• a plurality of sense amplifiers, each sense amplifier coupled to an a respective one of the column multiplexers;
• and
• a plurality of de-biasing circuits, each de-biasing circuit coupled to an output of a respective one of the sense amplifiers, wherein each de-biasing circuit comprises a XOR or XNOR logic gate having first and second inputs and an output and data latch having a data input and a data output, wherein first input of the logic gate is coupled to the output of the respective sense amplifier and the second input is coupled to the data output of the data latch;
• and
• a controller, the controller operable to control the PUF generator to output a vector of PUF bits, outputs for producing the PUF bits being produced at the data output of the data latches of the de-biasing circuits, wherein each output for producing the PUF bit is dependent on more than one sensed bit from the bit generating cells such that sensing bias of the sense amplifiers is reduced.