Digital signature verification engine for reconfigurable circuit devices

One or more non-transitory computer-readable storage mediums having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:

• configuring a reconfigurable circuit device to operate as a signature verification engine for a bit stream, the reconfigurable circuit device including a plurality of digital signal processing (DSP) blocks and a plurality of logic elements (LEs);
• generating a hash of a bit stream;
• and
• performing a signature verification for the bit stream utilizing the signature verification engine;
• wherein the signature verification engine includes a hybrid multiplication unit, the hybrid multiplication unit combining a set of the plurality of LEs and a set of the plurality of DSPs to multiply operands for the signature verification.

A computing system comprising:

• one or more processors;
• dynamic random access memory (DRAM) for storage of data;
• and
• an FPGA (Field Programmable Gate Array), the FPGA including:
• a block random access memory (BRAM),
• a plurality of digital signal processing (DSP) blocks, and
• a plurality of logic elements (LEs);
• wherein one or more processors are to configure the FPGA as an ECDSA (Elliptic Curve Digital Signature Algorithm) engine for signature verification of a bit stream, the ECDSA engine including:
• a hybrid multiplication unit, the hybrid multiplication unit combining a set of the plurality of LEs and a set of the plurality of DSPs to multiply operands for the signature verification.