Low latency post-quantum signature verification for fast secure-boot

An electronic device, comprising:

• a processor;
• and
• a hardware accelerator for an authentication logic, the hardware accelerator comprising:
• a computer readable memory;
• an XMSS verification manager logic to manage XMSS verification functions;
• a one-time signature and public key generator logic;
• a chain function logic to implement chain function algorithms;
• a low latency SHA3 hardware engine;
• and
• a register bank communicatively coupled to the XMSS verification manager logic.