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US 2019/0319782 A1Published application
Combined sha2 and sha3 based xmss hardware accelerator
AssigneeIntel Corporation
InventorsSANTOSH GHOSH, Vikram Suresh, Sanu Mathew, Manoj Sastry, Andrew H. Reinders, Raghavan Kumar, Rafael Misoczki
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Abstract
In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.
Claims20
An apparatus, comprising:
- a computer readable memory;
- an XMSS operations logic to manage XMSS functions;
- a chain function controller to manage chain function algorithms;
- a secure hash algorithm-2 (SHA2) accelerator;
- a secure hash algorithm-3 (SHA3) accelerator;
- and
- a register bank shared between the SHA2 accelerator and the SHA3 accelerator.
4 more elements
An electronic device, comprising:
- a processor;
- and
- a hardware accelerator for an authentication logic, the hardware accelerator comprising:
- a computer readable memory;
- an XMSS operations logic to manage XMSS functions;
- a chain function controller to manage chain function algorithms;
- a secure hash algorithm-2 (SHA2) accelerator;
- a secure hash algorithm-3 (SHA3) accelerator;
- and
- a register bank shared between the SHA2 accelerator and the SHA3 accelerator.
7 more elements
Dependencies are inferred from the claim text.