Vertical transistors having improved control of parasitic capacitance and source/drain-to-channel resistance

A method of forming a semiconductor device, the method comprising:

• forming a channel fin structure across from a major surface of a substrate;
• forming a gate structure across from the major surface of the substrate and along a sidewall surface of the channel fin structure, wherein the gate structure comprises a gate structure top surface;
• forming a source or drain (S/D) region having a S/D region bottom surface, wherein a first portion of the S/D region extends over the channel fin structure, wherein a second portion of the S/D region extends over the gate structure;
• configuring a first portion of the S/D region bottom surface to have a first predetermined distance from a first portion of the gate structure top surface;
• and
• configuring a second portion of the S/D region bottom surface to have a second predetermined distance from a second portion of the gate structure top surface;
• wherein the first predetermined distance is less than the second predetermined distance.