US 2019/0319097 A1Published application

Tiled Lateral BJT

AssigneeSilanna Asia Pte Ltd

InventorsVadim Kushner, Nima Beikae

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Abstract

A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.

Claims20

Dependent claims

A transistor tile formed within a horizontal length, a horizontal width, and a vertical thickness, the transistor tile comprising:

a first collector region located within a first portion of the transistor tile;
a second collector region located within a second portion of the transistor tile;
a base region located within a central portion of the transistor tile, wherein the central portion is horizontally between the first and second portions, and a direction of a flow of a base-collector current is horizontal between the first and second collector regions and the base region;
and
an emitter region located within the central portion of the transistor tile, wherein a direction of a flow of a collector-emitter current is horizontal between the first and second collector regions and the emitter region, and a direction of a flow of a base-emitter current is horizontal through the base region;
wherein the direction of the flow of the base-emitter current is perpendicular to the direction of the flows of the base-collector current and the collector-emitter current.

3 more elements

A transistor tile comprising:

a first collector region longitudinally spanning a first side of the transistor tile;
a second collector region longitudinally spanning a second side of the transistor tile;
a base region located laterally between the first and second collector regions;
and
an emitter region located laterally between the first and second collector regions;
wherein the base region and emitter region are both centered on a longitudinally extending, laterally located midline of the transistor tile.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/955,040Filed 17 Apr 2018
Published: 17 Oct 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 62/127
Top-view geometrical layouts of the regions or the junctions: of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
H10D 10/061
Manufacture or treatment: of lateral BJTs
H10D 10/60
Bipolar junction transistors [BJT]: lateral BJTs
H10D 62/126
Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions: top-view geometrical layouts of…

Family

US 10,811,497 B2Related patent
US 2019/0319097 A1This patent

From the US filing history. Foreign family members aren’t listed.

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