Vfet devices with improved performance
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Juntao Li, Choonghyun Lee, Shogo Mochizuki
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Abstract
Vertical field effect transistor (VFET) structures and methods of fabrication with improved junction sharpness and reduced parasitic capacitance between the top source or drain and the surrounding metal gate includes a non-uniform top spacer in the top source or drain formed by an oxidation process. The top spacer has a thickness that is thinner at an interface between the top source or drain region and the vertically oriented channel region of the fin structure relative to the thickness of the top spacer layer away from the interface.
Claims20
A method for forming a VFET structure, the method comprising:
- forming a top sacrificial spacer in a recessed dummy gate such that the top sacrificial spacer is adjacent to a fin and coplanar to a top surface of the fin;
- epitaxially growing a top source or drain onto the top surface of the fin such that a gap is formed between the top source or drain and the top sacrificial spacer;
- and
- oxidizing a surface of the top source or drain to form an oxide spacer layer thereon, wherein the oxide spacer layer has a thickness that is thinner at an interface between the top source or drain region and the vertically oriented channel region of the fin structure relative to the thickness of the top spacer layer away from the interface.
A method of forming a VFET structure, the method comprising:
- providing an intermediate structure comprising:
- a substrate, a bottom source or drain layer on the substrate;
- a fin extending vertically from and in contact with the bottom source or drain layer, wherein the fin includes a hardmask thereon;
- a bottom spacer on the bottom source or drain layer adjacent the fin;
- a recessed dummy gate about the fin;
- a top nitride spacer layer filling the recessed dummy gate, wherein the nitride top spacer layer has a surface coplanar to the top surface of the fin;
- and
- an interlayer dielectric coplanar with a top surface of the hardmask;
- selectively removing the hardmask and the interlayer dielectric to expose a top surface of the fin;
- epitaxially growing a top source or drain on the top surface of the fin such that a gap is formed between the top source or drain and the top sacrificial spacer;
- oxidizing a surface of the top source to form a top oxide spacer layer therein, wherein the top oxide spacer layer has a thickness that is thinner at an interface between the top source or drain region and the top surface of the fin structure relative to the thickness of the top oxide spacer layer away from the interface.
The method of claim 0, wherein the top source or drain comprises a diamond-shape.
A vertical field effect transistor (VFET) structure comprising:
- a top source or drain region extending from a vertically oriented channel region of a fin structure;
- and
- a top oxide spacer layer about the top source or drain region, the top oxide spacer having a thickness that is thinner at an interface between the top source or drain region and the vertically oriented channel region of the fin structure relative to the thickness of the top spacer layer away from the interface.
Dependencies are inferred from the claim text.