Integrated rf front end system

A multi-layer semiconductor package supporting a plurality of devices, the multi-layer semiconductor package comprising:

• a semiconductor wafer including a high-resistivity substrate of a first doping type;
• a transistor sub-collector region of a second doping type disposed at least partially below a top plane of the semiconductor wafer, the transistor sub-collector region forming a portion of a transistor;
• a low-resistivity epitaxial layer of the second doping type disposed above the top plane of the semiconductor wafer;
• a low-resistivity well providing at least one device from the plurality of devices with at least partial electrical isolation from the transistor;
• and
• a trench between the transistor sub-collector region and the low-resistivity well, the trench configured to impede a movement of carriers in the high-resistivity substrate.

A multi-layer semiconductor package supporting a plurality of devices, the multi-layer semiconductor package comprising:

• a semiconductor wafer including a high-resistivity substrate of a first doping type;
• a triple-well transistor disposed at least partially below a top plane of the semiconductor wafer;
• a low-resistivity epitaxial layer of a second doping type disposed above the top plane of the semiconductor wafer;
• a low-resistivity well providing at least one device from the plurality of devices with at least partial electrical isolation from the triple-well transistor;
• and
• a trench between the triple-well transistor and the low-resistivity well, the trench configured to impede a movement of carriers in the high-resistivity substrate.

A method of fabricating a multi-layer semiconductor package supporting a plurality of devices, the method comprising:

• forming a high-resistivity substrate of a first doping type within a semiconductor wafer;
• forming a triple-well transistor on the high-resistivity substrate, at least a portion of the triple-well transistor disposed below a top plane of the semiconductor wafer;
• forming a low-resistivity epitaxial layer of a second doping type above the top plane of the semiconductor wafer;
• implanting a low-resistivity well within the semiconductor wafer, the low-resistivity well providing at least one device from the plurality of devices with at least partial electrical isolation from the triple-well transistor;
• and
• etching a trench between the triple-well transistor and the low-resistivity well, the trench configured to impede a movement of carriers in the high-resistivity substrate.