US 2019/0319047 A1Published application

Semiconductor device

AssigneeRenesas Electronics Corporation

InventorsKazuya UEJIMA, Kazuhiro KOUDATE

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Abstract

Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.

Claims20

Dependent claims

A semiconductor device comprising:

a first logic circuit connected between a first power supply line and a first ground line;
a second logic circuit connected to a second power supply line, the second logic circuit being configured to receive an input signal from the first logic circuit;
a switch element connected between the second logic circuit and a second ground line;
a first transistor configuring the first logic circuit;
and
a second transistor configuring the switch element,
wherein the first transistor includes:
a support substrate;
a first semiconductor layer arranged over the support substrate through a first insulating layer;
a first source region, a first drain region and a first channel formation region formed inside the first semiconductor layer;
and
a first gate electrode arranged over the first channel formation region through a first gate insulating film,
the second transistor includes:
the support substrate, a second source region and a second drain region;
a second channel formation region arranged between the second source region and the second drain region;
and
a second gate electrode arranged over the second channel formation region through a second gate insulating film, and
an impurity concentration of the second channel formation region is higher than an impurity concentration of the first channel formation region.

15 more elements

A semiconductor device comprising:

a first logic circuit connected between a first power supply line and a first ground line;
a second logic circuit connected to a second power supply line, the second logic circuit being configured to receive an input signal from the first logic circuit;
a switch element connected between the second logic circuit and a second ground line;
a first transistor of a first conductive type configuring the first logic circuit;
and
a second transistor of the first conductive type configuring the switch element,
wherein the first transistor includes:
a support substrate;
a first semiconductor layer arranged over the support substrate through a first insulating layer;
a first source region of the first conductive type, a first drain region of the first conductive type and a first channel formation region formed inside the first semiconductor layer;
and
a first gate electrode arranged over the first channel formation region through a first gate insulating film,
the second transistor includes:
the support substrate;
a second semiconductor layer arranged over the support substrate through a second insulating layer;
a second source region of the first conductive type, a second drain region of the first conductive type and a second channel formation region formed inside the second semiconductor layer;
and
a second gate electrode arranged over the second channel formation region through a second gate insulating film,
a second power supply voltage supplied to the second power supply line is higher than a first power supply voltage supplied to the first power supply line, and
a length of the second gate electrode is larger than a length of the first gate electrode.

17 more elements

A semiconductor device comprising:

a first logic circuit connected between a first power supply line and a first ground line;
a second logic circuit connected to a second power supply line, the second logic circuit being configured to receive an input signal from the first logic circuit;
a switch element connected between the second logic circuit and a second ground line;
a first transistor of a first conductive type configuring the first logic circuit;
and
a second transistor of the first conductive type configuring the switch element,
wherein the first transistor includes:
a support substrate;
a first semiconductor layer arranged over the support substrate through a first insulating layer;
a first source region of the first conductive type, a first drain region of the first conductive type and a first channel formation region formed inside the first semiconductor layer;
and
a first gate electrode arranged over the first channel formation region through a first gate insulating film,
the second transistor includes:
the support substrate;
a second source region of the first conductive type, a second drain region of the first conductive type and a second channel formation region formed inside the support substrate;
and
a second gate electrode arranged over the second channel formation region through a second gate insulating film,
a second power supply voltage supplied to the second power supply line is higher than a first power supply voltage supplied to the first power supply line, and
a length of the second gate electrode is larger than a length of the first gate electrode.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/361,878Filed 22 Mar 2019
Priority: JP 2018-07737513 Apr 2018
Published: 17 Oct 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10D 87/00
Integrated devices comprising both bulk components and either soi or sos components
H03K 3/012
Details: modifications of generator to improve response time or to decrease power consumption
H03K 3/35613
Using additional transistors in the input circuit: the input circuit having a differential configuration
H03K 3/356165
Using complementary field-effect transistors: using additional transistors in the feedback circuit

Family

US 10,879,271 B2Related patent
US 2019/0319047 A1This patent

From the US filing history. Foreign family members aren’t listed.

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