US 2019/0319037 A1Published application

Method of manufacturing memory device

AssigneeWinbond Electronics Corp.

InventorsChung-Hsien Liu, Chun-Hsu Chen, Lu-Ping Chiang

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Abstract

Provided is a method of manufacturing a memory device including following steps. A substrate including an active region and a periphery region. A stack layer is formed on the substrate. A first trench is formed in the substrate and the stack layer in the active region. A first isolation structure is formed in the first trench. An ion implantation process is performed to form a doped first isolation structure. A first wet etching process is performed to remove a portion of the doped first isolation structure, so that a first recess is formed on the doped first isolation structure. A protection layer is formed on the substrate to at least cover sidewalls of the first recess. A second wet etching process is performed to remove the protection layer and another portion of the doped first isolation structure and deepen the first recess. A SICONI etching process is performed.

Claims10

Dependent claims

A method of manufacturing a memory device, comprising:

providing a substrate, comprising an active region and a periphery region;
forming a stack layer on the substrate;
forming a first trench in the substrate and the stack layer in the active region;
forming a first isolation structure in the first trench;
performing an ion implantation process to change the first isolation structure into a doped first isolation structure;
performing a first wet etching process to remove a portion of the doped first isolation structure, such that a first recess is formed on the doped first isolation structure;
forming a protection layer on the substrate to at least cover a sidewall of the first recess;
performing a second wet etching process to remove the protection layer and another portion of the doped first isolation structure, such that the first recess is deepened;
and
performing a SICONI etching process to remove the doped first isolation structure on an upper sidewall of the first trench.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/215,666Filed 11 Dec 2018
Priority: TW 10711293116 Apr 2018
Published: 17 Oct 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10B 41/42
Characterised by the peripheral circuit region: simultaneous manufacture of periphery and memory cells
H10W 10/014
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 41/47
Comprising only one type of peripheral transistor: with a floating-gate layer also being used as part of the peripheral transistor

Family

US 10,566,337 B2Related patent
US 2019/0319037 A1This patent

From the US filing history. Foreign family members aren’t listed.

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