3d memory having plural lower select gates

A device, comprising:

• a memory including a block of vertical channel structures, the block of vertical channel structures including a plurality of sub-blocks;
• sub-blocks in the plurality of sub-blocks each comprising
• an upper select line for vertical channel structures in the sub-block, the upper select line comprising a conductive strip in an upper level;
• word lines for vertical channel structures in the sub-block, the word lines comprising conductive strips in intermediate levels below the upper level;
• a first lower select line for vertical channel structures in the sub-block, the first lower select line comprising a conductive strip in a first lower level below the intermediate levels;
• a second lower select line for vertical channel structures in the sub-block, the second lower select line comprising a conductive strip in a second lower level below the first lower level;
• and
• control circuitry configured to apply voltages to the upper select lines, to the word lines and to the first and second lower select lines in the plurality of sub-blocks.

A device, comprising:

• a 3D NAND memory, including a block of vertical NAND strings, the block of vertical strings including a plurality of sub-blocks;
• sub-blocks in the plurality of sub-blocks each a plurality of NAND strings comprising
• an upper select line in an upper level;
• word lines in intermediate levels below the upper level;
• a first lower select line in a first lower level below the intermediate levels;
• a second lower select line in a second lower level below the first lower level;
• and
• control circuitry configured to apply voltages to the upper select lines, to the word lines and to the first and second lower select lines in the plurality of sub-blocks.