Memory devices and methods for fabricating the same

A method for fabricating a memory device, comprising:

• forming an isolation region in a substrate to define active regions that are arranged in a first direction;
• forming pairs of word lines in the substrate, wherein each of the active regions corresponds to one pair of word lines, and each of the active regions has a drain region between one word line of the pairs of word lines and the isolation region and a source region between one of the pairs of word lines;
• forming a first dielectric layer on the substrate to cover the pairs of word lines, wherein the first dielectric layer has a first opening exposing the isolation region and the drains of neighboring two of the active regions;
• filling a lower portion of the first opening with a first conductive material layer;
• conformally forming a lining layer over sidewalls of an upper portion of the first opening and a top surface of the first conductive material layer;
• filling the upper portion of the first opening with a second conductive material layer after forming the lining layer;
• performing an etch-back process on the second conductive material layer and the lining layer in the first opening to form a recess;
• conformally forming a protection layer on sidewalls and a bottom portion of the recess and a top surface of the first dielectric layer;
• performing an etching process to form a second opening that penetrates through the protection layer, the second conductive material layer, the lining layer and the first conductive layer and to expose the isolation layer;
• forming a second dielectric layer that covers the protection layer and the first dielectric layer and entirely fills the second opening;
• and
• removing portions of the first dielectric layer, the protection layer and the second dielectric layer so that a top surface of the second conductive material layer, a top surface of the first dielectric layer and a top surface of the second dielectric layer in the second opening are coplanar.