Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections

A method of cross-connecting gates of semiconductor devices formed in a circuit, comprising:

• forming a P-type diffusion region having a longitudinal axis disposed in a first direction above a substrate;
• forming an N-type diffusion region having a longitudinal axis disposed in the first direction above the substrate;
• forming a plurality of gates above the substrate, each having a longitudinal axis and disposed in a second direction substantially orthogonal to the first direction;
• cutting a first gate among the plurality of gates to form a first gate cut area having a first latitudinal axis in the second direction and disposed in a first routing track among a plurality of routing tracks;
• forming a first metal line in a first metal layer extending in the first direction in the first routing track extending in the first direction in a non-diffusion region between the P-type diffusion region and the N-type diffusion region, the first metal line electrically coupled to a second gate among the plurality of gates to form a second active gate in the second gate;
• cutting the second gate to form a second gate cut area having a second latitudinal axis in the second direction substantially parallel to the first latitudinal axis and disposed in a second routing track among the plurality of routing tracks, the second latitudinal axis of the second gate cut area offset from the first latitudinal axis of the first gate cut area in the second direction;
• forming a second metal line in the first metal layer extending in the first direction in the second routing track in the non-diffusion region, the second metal line electrically coupled to the first gate to form a first active gate in the first gate;
• and
• forming a first cross-connect metal line disposed in a second metal layer above the first metal layer and extending in the second direction, the first cross-connect metal line electrically coupled to the first metal line and the second metal line electrically coupling the second active gate to the first active gate.

A latch circuit, comprising:

• a P-type diffusion region disposed above a substrate and having a longitudinal axis in a first direction;
• an N-type diffusion region disposed above the substrate and having a longitudinal axis in the first direction;
• a non-diffusion region disposed above the substrate between the P-type diffusion region and the N-type diffusion region;
• a first gate having a longitudinal axis and disposed in a second direction substantially orthogonal to the first direction;
• A SECOND GATE HAVING A LONGITUDINAL AXIS SUBSTANTIALLY PARALLEL TO THE LONGITUDINAL AXIS OF THE FIRST GATE, THE SECOND GATE DISPOSED IN THE SECOND DIRECTION SUBSTANTIALLY ORTHOGONAL TO THE FIRST DIRECTION;
• a first P-type metal-oxide semiconductor (MOS) (PMOS) transistor comprising a first PMOS active gate in the first gate, the first PMOS active gate in the non-diffusion region, a first PMOS source/drain in the P-type diffusion region, and a first PMOS drain/source in the P-type diffusion region;
• a first N-type MOS (NMOS) transistor comprising a first NMOS active gate in the first gate, the first NMOS active gate in the N-type diffusion region, a first NMOS source/drain in the N-type diffusion region, and a first NMOS drain/source in the N-type diffusion region;
• a first gate cut area disposed in the first gate in the non-diffusion region between the first PMOS active gate and the first NMOS active gate and electrically isolating the first PMOS active gate and the first NMOS active gate;
• a second PMOS transistor comprising a second PMOS active gate in the second gate, the second PMOS active gate in the P-type diffusion region and electrically coupled to the first NMOS active gate, a second PMOS source/drain in the P-type diffusion region, and a second PMOS drain/source in the P-type diffusion region;
• a second NMOS transistor comprising a second NMOS active gate in the second gate, the second NMOS active gate in the non-diffusion region and electrically coupled to the first PMOS active gate, a second NMOS source/drain in the N-type diffusion region, and a second NMOS drain/source in the N-type diffusion region;
• and
• a second gate cut area disposed in the second gate in the non-diffusion region between the second PMOS active gate and the second NMOS active gate and electrically isolating the second PMOS active gate and the second NMOS active gate.