US 2019/0318986 A1 · Semiconductor Device Having Via Sidewall Adhesion With Encapsulant

Abstract

Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.

Claims20

Dependent claims

A method, comprising:

forming a die, the die comprising a pad and a passivation layer over the pad;
forming a first opening through the passivation layer;
depositing a resist layer over the die;
patterning the resist layer to form a second opening aligned to the first opening;
forming a via in the second opening, the via having a first co-efficient of thermal expansion (CTE);
forming a solder cap on the via, wherein a first material of the solder cap flows to a sidewall of the via;
and
encapsulating the via in a first encapsulant, wherein the first encapsulant has a second CTE and a curing temperature, wherein a ratio of the second CTE and first CTE is less than 2.5:1 or the first curing temperature is less than 250° C.

5 more elements

Dependencies are inferred from the claim text.

Semiconductor Device Having Via Sidewall Adhesion With Encapsulant

Life of this patent

Semiconductor Device Having Via Sidewall Adhesion With Encapsulant

Life of this patent

Abstract

Claims20