MASKLESS EPITAXIAL GROWTH OF PHOSPHORUS-DOPED Si AND BORON-DOPED SiGe (Ge) FOR ADVANCED SOURCE/DRAIN CONTACT

A method for forming a transistor having reduced parasitic contact resistance, the method comprising:

• forming an nFET device and a pFET device over a semiconductor structure;
• forming an interlayer dielectric (ILD) over the nFET and pFET devices;
• selectively recessing the ILD to expose a top surface of source/drain regions of the nFET and the pFET devices;
• forming a GeO2 layer over the source/drain regions of the nFET and pFET devices, the GeO2 layer over the source/drain regions of the pFET device being converted to a SiO2 overlayer and a Ge-rich underlayer via a selective Ge condensation process;
• and
• removing the remaining GeO2 layer to expose a top surface of the source/drain regions of the nFET.

A semiconductor structure for constructing a transistor having reduced parasitic contact resistance, the semiconductor structure comprising:

• a first device disposed over a semiconductor structure;
• a second device disposed adjacent the first device, the first and second devices separated from each other by a sidewall trench isolation (STI) structure;
• an interlayer dielectric (ILD) disposed over the first and second devices;
• recesses disposed within the ILD to expose the source/drain regions of the first device and the source/drain regions of the second device;
• a first dielectric layer disposed over the ILD and the top surfaces of the source/drain regions of the first and second devices, a chemical interaction between the first dielectric layer and the source/drain regions of the second device resulting in second dielectric layers disposed over the source/drain regions of the second device;
• and
• an epitaxial layer disposed over the source/drain regions of the first device after removing remaining portions of the first dielectric layer.