Variable gate lengths for vertical transistors

A semiconductor structure comprising:

• a first vertical field effect transistor (FET) formed on a semiconductor substrate and a second vertical FET formed on the semiconductor substrate;
• the first vertical FET with a gate height that is not co-planar to a gate height of the second vertical FET;
• the first vertical FET comprising a first layer above a gate on the first vertical FET;
• and
• the second vertical FET comprising a second layer above a gate on the second vertical FET;
• and
• wherein the bottom of the gate on the first vertical FET is co-planar with the bottom of the gate on the second vertical FET.

A method for fabricating a vertical field-effect transistor (FET) structure, the method comprising:

• prior to depositing a gate of a first vertical FET on a semiconductor substrate, depositing a first layer of the first vertical FET on the semiconductor substrate;
• prior to depositing a gate of a second vertical FET on the semiconductor substrate, depositing a second layer of the second vertical FET on the semiconductor substrate;
• etching the first layer of the first vertical FET to a lower height than the second layer of the second vertical FET;
• depositing a gate material of both the first vertical FET and the second vertical FET;
• and
• etching the gate material of both the first vertical FET and the second vertical FET to a co-planar height.