High threshold voltage fet with the same fin height as regular threshold voltage vertical fet

A semiconductor device comprising:

• a first vertical fin with a first gate stack and a second vertical fin with a second gate stack, wherein the first vertical fin and the second vertical fin are substantially a same fin length, wherein the first gate stack has a first gate length and the second gate stack has a second gate length, the second gate length being greater than the first gate length;
• a bi-layer top spacer formed on top of the first and second gate stacks;
• a first bottom S/D directly on sides of the first vertical fin and a second bottom S/D region directly on sides of the second vertical fin;
• and
• a first top S/D region adjacent to the first vertical fin and a second top S/D region adjacent to the second vertical fin.

A method of forming a semiconductor device, the method comprising:

• forming a first vertical fin with a first gate stack and a second vertical fin with a second gate stack, wherein the first vertical fin and the second vertical fin are substantially a same fin length, wherein the first gate stack has a first gate length and the second gate stack has a second gate length, the second gate length being greater than the first gate length;
• forming a bi-layer top spacer on top of the first and second gate stacks;
• forming a first bottom S/D region directly on sides of the first vertical fin and a second bottom S/D region directly on sides of the second vertical fin;
• and
• forming a first top S/D region adjacent to the first vertical fin and a second top S/D region adjacent to the second vertical fin.