Memory device including load generator and method of operating the same

A memory controller configured to control a memory device, the memory controller comprising:

• a load generator configured to output memory test loads for a plurality of first memory accesses directed to the memory device;
• an interface circuit configured to receive the memory test loads from the load generator, the memory test loads mimicking memory access requests for a plurality of second memory devices accesses directed to the memory device from a plurality of master devices;
• and
• processing circuits configured to,
• receive the memory test loads from the interface circuit, and
• process the memory test loads such that memory operations associated with the plurality of first memory accesses are performed in the memory device,
• wherein, in response to a test enable signal,
• the load generator is further configured to output the memory test loads, the memory test loads having a data format equivalent to a data format of the memory access requests from the plurality of master devices, and
• the interface circuit is further configured to receive the memory test loads from the load generator, without receiving the memory access requests from the plurality of master devices.

A method of operating a memory device, the method comprising:

• receiving an enable signal for a test of the memory device;
• generating, by a load generator, memory test loads for memory accesses directed to the memory device based on the enable signal, the generating the memory test loads including outputting the memory test loads at a constant bandwidth rate;
• and
• processing, by a memory controller of the memory device, the memory test loads, the processing the memory test loads including performing memory operations associated with memory accesses corresponding to the memory test loads.