Memory management method, memory storage device and memory control circuit unit

A memory storage device comprising:

• a connection interface unit configured to couple to a host system;
• a rewritable non-volatile memory module comprising a plurality of memory cells;
• and
• a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module,
• wherein the memory control circuit unit is configured to send a write command sequence which indicates to program first data into a plurality of first memory cells among the memory cells, such that the programmed first memory cells have a plurality of states, wherein each of the plurality of states corresponds to a default bit value,
• wherein the memory control circuit unit is further configured to send a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level,
• wherein the memory control circuit unit is further configured to obtain first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence, and
• wherein the memory control circuit unit is further configured to adjust the first read voltage level according to the first count information and default count information corresponding to the first read voltage level.

A memory control circuit unit configured to control a rewritable non-volatile memory module comprising a plurality of memory cells, the memory control circuit unit comprising:

• a host interface configured to couple to a host system;
• a memory interface configured to couple to the rewritable non-volatile memory module;
• and
• a memory management circuit coupled to the host interface and the memory interface,
• wherein the memory management circuit is configured to send a write command sequence which indicates to program first data into a plurality of first memory cells among the memory cells, such that the programmed first memory cells have a plurality of states, wherein each of the plurality of states corresponds to a default bit value,
• wherein the memory management circuit is further configured to send a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level,
• wherein the memory management circuit is further configured to obtain first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence, and
• wherein the memory management circuit is further configured to adjust the first read voltage level according to the first count information and default count information corresponding to the first read voltage level.