Ferroelectric-based memory cell usable in on-logic chip memory

A semiconductor device comprising:

• a plurality of memory cells, each of the plurality of memory cells including at least one ferroelectric transistor (FE-transistor) and at least one selection transistor coupled with the FE-transistor, the FE-transistor including a transistor and a ferroelectric capacitor for storing data, the ferroelectric capacitor including at least one ferroelectric material;
• and
• a plurality of selection lines coupled with the plurality of memory cells.

A method for operating a memory cell comprising:

• programming the memory cell, the memory cell including a ferroelectric transistor (FE-transistor) and a selection transistor coupled with the FE-transistor, the FE-transistor including a transistor and a ferroelectric capacitor for storing data, the ferroelectric capacitor including at least one ferroelectric material, the transistor of the FE-transistor including a source, a drain and a gate coupled with the ferroelectric capacitor, the selection transistor including a selection transistor source, a selection transistor drain and a selection transistor gate, a write port of the memory cell being selected from the selection transistor source and the selection transistor drain, the step of programming the memory cell including
• providing a selection signal to the selection transistor gate of the memory cell, the selection signal being not more than a logic supply voltage;
• providing a program voltage to the write port while the source and drain of the transistor of the FE-transistor are at ground, the program voltage being not more than the logic supply voltage.