Parallelism in disparity map generation
AssigneeIntel Corporation
InventorsWei-Yu Tsai, Amit Aneja, Maciej Adam Kaminski, Dhawal Srivastava, Jayaram Puttaswamy, Mithali Shivkumar
Life of this patent
Estimating the term…
Loading patent…
AssigneeIntel Corporation
InventorsWei-Yu Tsai, Amit Aneja, Maciej Adam Kaminski, Dhawal Srivastava, Jayaram Puttaswamy, Mithali Shivkumar
Estimating the term…
Input images are partitioned into non-overlapping segments perpendicular to a disparity dimension of the input images. Each segment includes a contiguous region of pixels spanning from a first edge to a second edge of the image, with the two edges parallel to the disparity dimension. In some aspects, contiguous input image segments are assigned in a “round robin” manner to a set of sub-images. Each pair of input images generates a corresponding pair of sub-image sets. Semi-global matching processes are then performed on pairs of corresponding sub-images generated from each input image. The SGM processes may be run in parallel, reducing an elapsed time to generate respective disparity sub-maps. The disparity sub-maps are then combined to provide a single disparity map of equivalent size to the original two input images.
A system to generate a disparity map, comprising:
A method of generating a disparity map with hardware processing circuitry, comprising:
A computer readable storage medium comprising instructions that when executed configure hardware processing circuitry to perform operations to generate a disparity map, the operations comprising:
Dependencies are inferred from the claim text.