Histogram Statistics Circuit and Multimedia Processing System

A multimedia processing system, comprising a memory, a histogram statistics circuit, and a processor, wherein

• the memory is configured to store multimedia data;
• the histogram statistics circuit is configured to:
• obtain the multimedia data from the memory, and perform histogram statistics on the multimedia data, to generate a statistical result;
• and
• the processor is configured to process the multimedia data based on the statistical result and a histogram application algorithm;
• wherein
• the histogram statistics circuit comprises a counter cache, a controller, a parsing circuit, a matching-and-decoding circuit, and a count value updating circuit, wherein the controller is coupled to the counter cache, the parsing circuit, and the matching-and-decoding circuit, and the count value updating circuit is coupled between the counter cache and the matching-and-decoding circuit;
• the counter cache is configured to cache Y groups of counters, wherein each group of counters comprises at least one counter and each counter corresponds to one current count value, and Y is a positive integer greater than 1;
• the controller is configured to control the memory to group pixels in the multimedia data, to obtain M groups of data;
• the parsing circuit is configured to perform the following step:
• obtaining an ith group of data from the M groups of data, and parsing each pixel value in the ith group of data, to determine X groups of counters that match the ith group of data in the Y groups of counters stored in the counter cache, wherein X is a positive integer and 1≤X≤Y;
• and the parsing circuit repeatedly performs the step until i=M, wherein i is a natural number whose starting value is 1 and is increased by 1 in each iterative process;
• the controller is further configured to control, based on the X groups of counters determined by the parsing circuit, the matching-and-decoding circuit to match the ith group of data with each of the X groups of counters in X clock cycles;
• the matching-and-decoding circuit is configured to perform the following step:
• in a jth clock cycle, matching each pixel in the ith group of data with a jth group of counters in the X groups of counters, and instructing, based on a matching result, the count value updating circuit to update a count value of the jth group of counters;
• and the matching-and-decoding circuit repeatedly performs the step until j=X, wherein j is a natural number whose starting value is I and is increased by 1 in each iterative process;
• and
• the count value updating circuit is configured to:
• read a current count value of the jth group of counters from the counter cache in the jth clock cycle, update the current count value of the jth group of counters based on the matching result indicated by the matching-and-decoding circuit, to obtain an updated count value of the jth group of counters, and write back the updated count value of the jth group of counters into the jth group of counters in the counter cache.