Neuromorphic circuit having 3d stacked structure and semiconductor device having the same

A neuromorphic circuit comprising:

• a synaptic core layer comprising a plurality of synaptic cores, each synaptic core comprising a plurality of neural circuits and a memory array storing synapse information;
• global routers each configured to determine an information transfer path between the synaptic cores;
• and
• a global interconnect layer forming a physical transfer path between the global routers,
• wherein the synaptic core layer and the global interconnect layer are arranged in a stack structure, and information from a synaptic core of the synaptic core layer is transferred to the global interconnect layer via one or more through electrodes.

An operating method of a semiconductor device, wherein the semiconductor device comprises a plurality of semiconductor layers with circuitry communicating with each other via a through silicon via (TSV), the operating method comprising:

• transferring information from a first synaptic core including a plurality of neural circuits formed in a first semiconductor layer to a first router associated with the first synaptic core;
• transferring the information from the first router to a second router via an interconnect formed in a second semiconductor layer stacked on the first semiconductor layer;
• and
• transferring the information from the second router to a second synaptic core formed in a third semiconductor layer stacked on the second semiconductor layer, the second synaptic core being associated with the second router.

A semiconductor device comprising:

• a first semiconductor layer comprising processing elements of a parallel processing system;
• a second semiconductor layer stacked on the first semiconductor layer and comprising an interconnect forming a physical transfer path between processing elements;
• a third semiconductor layer stacked on the second semiconductor layer and comprising processing elements;
• and
• one or more through electrodes disposed within at least one of the first, second and third layers, through which information is transferred between the first through third semiconductor layers,
• wherein information from a first processing element in the first semiconductor layer is transferred to a second processing element in the third semiconductor layer via the one or more through electrodes and the interconnect of the second semiconductor layer.