Method for triggering and detecting a malicious circuit in an integrated circuit device

A method for triggering and detecting a malicious circuit on an integrated circuit device, the method comprising:

• scanning in a first run of test patterns to logic circuits on the integrated circuit device using logic built-in self-test (LBIST), the first run of test patterns comprising a plurality of test patterns, each test pattern of the first run of test patterns comprising a plurality of bits, a first portion of the plurality of bits being bits that do not influence a value of a resulting first test output vector, and a second portion of the plurality of bits being bits that will influence the value of the first test output vector;
• scanning out the first test output vectors from the first run of test patterns;
• comparing the value of the first test output vectors to first expected values;
• changing bit values of the first portion of the plurality of bits for each test pattern of the first run of test patterns to generate a second run of test patterns;
• scanning in the second run of test patterns to the logic circuits on the integrated circuit device;
• scanning out the second test output vectors resulting from the second run of test patterns;
• and
• comparing a value of the second run of test patterns to second expected values.

A method for triggering and detecting a malicious circuit on an integrated circuit device, the method comprising:

• scanning in a first run of test patterns to logic circuits on the integrated circuit device using logic built-in self-test (LBIST), the first run of test patterns comprising a plurality of test patterns, each test pattern of the first run of test patterns comprising a plurality of bits, a first portion of the plurality of bits being bits that do not influence a value of a resulting first test output vector, and a second portion of the plurality of bits being bits that will influence the value of the first test output vector;
• scanning out the first test output vectors from the first run of test patterns;
• comparing the value of the first test output vectors to first expected values;
• changing bit values of the first portion of the plurality of bits for each test pattern of the first run of test patterns to generate a second run of test patterns;
• scanning in the second run of test patterns to the logic circuits on the integrated circuit device;
• scanning out the second test output vectors resulting from the second run of test patterns;
• comparing a value of the second run of test patterns to second expected values;
• and
• detecting the malicious hardware in response to comparing the values of the first and second test output vectors.