Techniques for control flow protection
AssigneeIntel Corporation
InventorsABHISHEK BASAK, RAVI SAHITA, VEDVYAS SHANBHOGUE
Life of this patent
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Abstract
Various embodiments are generally directed to techniques for control flow protection with minimal performance overhead, such as by utilizing one or more micro-architectural optimizations to implement a shadow stack (SS) to verify a return address before returning from a function call, for instance. Some embodiments are particularly directed to a computing platform, such as an internet of things (IoT) platform, that overlaps or parallelizes one or more SS access operations with one or more data stack (DS) access operations.
Claims25
An apparatus, comprising:
- a processor;
- and
- memory comprising instructions that when executed by the processor cause the processor to:
- determine to evict a cache line from a cache memory comprising a first cache line and a second cache line;
- preserve the first cache line in the cache memory based on determination of an association between the first cache line and a shadow stack;
- and
- select the second cache line to evict from the cache memory based on determination of no association between the second cache line and the shadow stack.
At least one non-transitory computer-readable medium comprising a set of instructions that, in response to being executed by a processor circuit, cause the processor circuit to:
- determine to evict a cache line from a cache memory comprising a first cache line and a second cache line;
- preserve the first cache line in the cache memory based on determination of an association between the first cache line and a shadow stack;
- and
- select the second cache line to evict from the cache memory based on determination of no association between the second cache line and the shadow stack.
A computer-implemented method, comprising:
- determining to evict a cache line from a cache memory comprising a first cache line and a second cache line;
- preserving the first cache line in the cache memory based on determination of an association between the first cache line and a shadow stack;
- and
- selecting the second cache line to evict from the cache memory based on determination of no association between the second cache line and the shadow stack.
Dependencies are inferred from the claim text.