High Performance Regularized Network-on-Chip Architecture

A non-transitory computer-readable medium comprising instructions that, when executed, are configured to cause one or more processors to:

• receive data regarding an integrated circuit and data regarding performance characteristics for a network-on-chip (NoC) to be designed;
• select source points and endpoints for the NoC based on the data regarding the integrated circuit and the data regarding performance characteristics for the NoC;
• determine routes between the source points and the endpoints;
• determine whether an expected performance level associated with the routes is within a threshold range of a performance level defined by the performance characteristics;
• include the endpoints and the routes in the NoC;
• and
• generate instructions configured to cause circuitry corresponding to the NoC to be implemented on the integrated circuit.

An integrated circuit configured to:

• receive instructions regarding a NoC design;
• and
• implement circuitry corresponding to the NoC design, wherein the NoC design is determined by:
• determining a first portion of a plurality of registers to potentially be included in the NoC design;
• determining routing information regarding datapaths between registers of the first portion of the plurality of registers;
• determining an expected performance associated with the first portion of the plurality of registers;
• determining whether the expected performance is within a threshold range;
• and
• including the first portion of the plurality of registers and the datapaths in the NoC design after determining that the expected performance is within the threshold range.