Data processing system having a cache with a store buffer

In a data processing system having a central processing unit (CPU), a memory, a memory management unit (MMU), and a cache, a method comprising:

• providing, by the CPU, a store request having corresponding store data and a corresponding access address which indicates a memory location in the memory for storing the store data;
• providing, by the MMU, a memory coherency required attribute corresponding to the access address of the store request;
• determining whether the access address hits or misses in a cache array of the cache;
• when the store request results in a write-through store due to a cache hit in the cache array or results in a cache miss in the cache array, storing the corresponding access address and store data in a selected entry of the store buffer and storing a merge allowed indicator in the selected entry of the store buffer which indicates whether or not the selected entry of the store buffer is a candidate for merging, wherein the merge allowed indicator is determined based on the memory coherency required attribute from the MMU and a store buffer coherency enable control bit of the cache;
• and
• merging entries of the store buffer which include an asserted merge allowed indicator and share a memory line in the memory by combining store data of entries being merged into a single merged entry.

A data processing system, comprising:

• a memory;
• a central processing unit (CPU) configured to provide a store request having corresponding store data and a corresponding access address which indicates a memory location in the memory for storing the store data;
• a memory management unit (MMU) coupled to the CPU and configured to translate the access address of the store request into a physical address and provide the physical address and a memory coherency required attribute corresponding to the physical address of the store request;
• a cache coupled to the CPU, MMU, and memory, the cache having a cache array, store buffer, and a control register configured to store a store buffer coherency enable control bit, the cache configured to receive the physical address and the memory coherency required attribute from the MMU, and configured to, when the physical address results in a write-through store due to a cache hit or results in a cache miss, store the physical address and store data corresponding to the store request in a selected entry of the store buffer and store a merge allowed indicator in the selected entry of the store buffer corresponding to the store request which indicates whether or not the selected entry of the store buffer is a candidate for merging, wherein the merge allowed indicator is determined based on the memory coherency required attribute from the MMU and the store buffer coherency enable control bit of the control register;
• and
• store buffer merge circuitry configured to merge entries of the store buffer which include an asserted merge allowed indicator and share a memory line in the memory, wherein the store buffer merge circuitry is configured to merge entries of the store buffer by combining store data of entries being merged into a single merged entry.