Error-correcting code memory
AssigneeTexas Instruments Incorporated
InventorsIndu Prathapan, Prashanth Saraf, Desmond Pravin Martin Fernandes, Saket Jalan
Life of this patent
Estimating the term…
Abstract
In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.
Claims20
A memory controller comprising:
- read-modify-write logic configured to:
- receive a partial write data request that includes partial write data;
- retrieve read data from a memory device, in response to the partial write data request;
- and
- combine the read data and the partial write data to form combined data;
- error-correcting code check and repair logic coupled to the read-modify-write logic and configured to:
- generate a first error-correcting code for the read data;
- and
- check the read data for an error based on the first error-correcting code;
- and
- an error-correcting code generator coupled to the read-modify-write logic and configured to generate a second error-correcting code for the combined data such that the generation of the second error-correcting code and the check of the read data are performed concurrently.
A method comprising:
- receiving a write request that includes an address and a data set;
- retrieving, from a memory device, read data stored at the address and a first error-correcting code associated with the read data;
- checking accuracy of the read data using the first error-correcting code;
- combining the data set and the read data to produce combined data;
- and
- generating a second error-correcting code for the combined data concurrent with the checking of the accuracy of the read data.
A memory controller comprising:
- read-modify-write logic to:
- receive a partial write data request containing partial write data;
- receive, from a memory device, read data and a first error-correcting code associated with the read data in response to the partial write data request;
- and
- combine the partial write data and the read data to produce combined data;
- and
- error-correcting code check and repair logic coupled to the read-modify-write logic and configured to check the read data for an error based on the first error-correcting code such that the check of the read data for the error and the combination of the partial write data and the read data is performed concurrently.
Dependencies are inferred from the claim text.