Techniques for improved latency of thread synchronization mechanisms
AssigneeAdvanced Micro Devices, Inc.
InventorsAmin Farmahini-Farahani, David A. Roberts, Nuwan Jayasena
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AssigneeAdvanced Micro Devices, Inc.
InventorsAmin Farmahini-Farahani, David A. Roberts, Nuwan Jayasena
Estimating the term…
A memory fence or other similar operation is executed with reduced latency. An early fence operation is executed and acts as a hint to the processor executing the thread that executes the fence. This hint causes the processor to begin performing sub-operations for the fence earlier than if no such hint were executed. Examples of sub-operations for the fence include operations to make data written to by writes prior to the fence operation available to other threads. A resolving fence, which occurs after the early fence, performs the remaining sub-operations for the fence. By triggering some or all of the sub-operations for a memory fence that will occur in the future, the early fence operation reduces the amount of latency associated with that memory fence operation.
A method for executing a thread synchronization operation, the method comprising:
A system for executing a thread synchronization operation, the system comprising:
A system for executing a thread synchronization operation, the system comprising:
Dependencies are inferred from the claim text.